In some signal processing algorithms, basic operations include multiplications and additions. These operations are typically performed in the digital domain by a digital signal processor (DSP), central processing unit (CPU) or custom digital logic, operating on numeric digital data obtained by measurement of the original analog values. One digital logic element commonly incorporated in such operations is a multiply-accumulate unit or MAU, as known to those of skill in the art.
Among other uses, multiply accumulate units can be useful to implement matrix vector multipliers with which general linear transformations, such as for instance the discrete Fourier transform (DFT), can be implemented. Furthermore, multiply accumulate units can be used to implement finite impulse response filters (FIRs).
In communication systems such as wireless networks and digital subscriber line (DSL) links, sophisticated signal processing algorithms can be used to perform tasks such as channel equalization, synchronization and error-correction. In several of these systems the operation of equalization is performed by a linear operation. An example is the use of orthogonal frequency division multiplexing in wireless systems, and discrete-multi tone (DMT) in DSL systems.
In some communication systems, the speed is sufficiently high or the power budget sufficiently low that the use of digital logic to perform the required signal processing operations is prohibitively complex. Conventional attempts to overcome such problems are inefficient, ineffective and/or have undesirable side effects or other drawbacks with respect to at least one significant use case.
Embodiments of the invention are directed toward solving these and other problems individually and collectively.